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This paper proposes a down-sampled discrete-time internal-model-based controller in the synchronous reference frame with a reduced number of poles. This controller is suitable for three-phase pulsewidth modulation inverters with output transformer for double-conversion uninterruptible power supply applications. It is demonstrated that the use of a down-sampled rate and fewer poles in the internal model results in a number of benefits, among which are the following: 1) improvement of the transient response; 2) increase of the stability margin of the closed-loop system; 3) a straightforward implementation in fixed-point digital signal processor (DSP) and microcontroller implementation as well as a reduction of the required memory space; and 4) a simple solution for the saturation of the output transformer. As a result, it is possible to obtain output voltages with reduced total harmonic distortion while ensuring good transient performance for both linear and nonlinear loads. To confirm the advantages claimed for the proposed synchronous reference dq frame internal-model-based controller and to demonstrate the steady-state and transient performance under the test conditions of the International electrotechnical commission standard 62040-3, the experimental results from a 10-kVA space-vector-modulated three-phase inverter, which is fully controlled by a DSP TMS320F241, are presented.

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2120 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

A Three-Phase UPS That Complies

With the Standard IEC 62040-3

Fernando Botterón and Humberto Pinheiro

Abstract—This paper proposes a down-sampled discrete-time

internal-model-based controller in the synchronous reference

frame with a reduced number of poles. This controller is suit-

able for three-phase pulsewidth modulation inverters with output

transformer for double-conversion uninterruptible power supply

applications. It is demonstrated that the use of a down-sampled

rate and fewer poles in the internal model results in a number

of beneﬁts, among which are the following: 1) improvement of

the transient response; 2) increase of the stability margin of

the closed-loop system; 3) a straightforward implementation in

ﬁxed-point digital signal processor (DSP) and microcontroller

implementation as well as a reduction of the required mem-

ory space; and 4) a simple solution for the saturation of the

output transformer. As a result, it is possible to obtain output

voltages with reduced total harmonic distortion while ensuring

good transient performance for both linear and nonlinear loads.

To conﬁrm the advantages claimed for the proposed synchro-

nous reference dq frame internal-model-based controller and to

demonstrate the steady-state and transient performance under the

test conditions of the International Electrotechnical Commission

Standard 62040-3, the experimental results from a 10-kVA

space-vector-modulated three-phase inverter, which is fully con-

trolled by a DSP TMS320F241, are presented.

Index Terms—Digital control, discrete-time control, internal

model principle, power transformers, uninterruptible power

systems (UPSs).

I. I NTRODUCTION

HE USE of uncontrolled rectiﬁers within critical loads,

e.g., in computers and medical equipment, requires unin-

terruptible power supplies (UPSs) that are capable of maintain-

ing low total harmonic distortion (THD) at the output voltages

even under highly distorted load currents [1]. These types of

loads distort the UPS output voltages as a result of unbalanced

nonlinear currents drawn by them, thus causing voltage drops

across the output inductance–capacitance (LC ) ﬁlter, which is

used to attenuate the pulsewidth-modulation (PWM) inverter

high-frequency harmonics. This becomes a concern in medium-

and high-power UPS, where the switching frequency is low

to limit the switching losses. Other factors also contribute to

UPS output voltage distortion. Among them are the inherent

Manuscript received November 7, 2005; revised February 28, 2006. This

work was supported in part by CAPES and in part by CNPq.

F. Botterón is with the Departamento de Electrónica, Facultad de Ingeniería,

Universidad Nacional de Misiones, Obera 3360, Argentina (e-mail: botteron@

gmail.com).

H. Pinheiro is with the Power Electronics and Control Research Group,

Federal University of Santa Maria, Santa Maria 97105-900, Brazil (e-mail:

humberto@ctlab.ufsm.br).

Color versions of one or more of the ﬁgures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identiﬁer 10.1109/TIE.2007.894782

nonlinearities of the PWM inverter, ﬂuctuations of the dc

bus voltage, and power semiconductor voltage drops. More-

over, transformerless UPSs are susceptible to interference from

spikes and transients caused by assorted devices connected to

the utility grid. These interferences, transferred through the

UPS to the load, reduce the UPS output voltage quality. Thus,

UPSs with output transformer provide a safer and more robust

solution than transformerless UPSs since the transformer offers

a galvanic isolation to the load from undesirable disturbances

of the main supply [2].

In digitally controlled systems, quantization of the analog-

to-digital converters, digital PWMs, and roundoff resulting

from ﬁxed-point arithmetic can generate errors that result in

a dc component at the inverter output voltage. These errors,

added to the inevitable nonideal features of real live circuit

implementation and ampliﬁed by an inappropriate selection

of the controller, can lead the output transformer to saturate,

degrading the overall performance of the system [13]–[15]. It is

important to point out that a standard such as the International

Electrotechnical Commission (IEC) 62040-3 recommends that

the output voltage dc component shall be less than 0.1% of

its root mean square (rms) rated value and speciﬁes that the

distortion factor "D" of sinusoidal UPS output voltages must

to be less than 8%. To deal with these issues, many discrete-

time control structures for single-phase and three-phase UPSs

are reported in the literature.

With the well-known Repetitive Controller [4]–[6], which

is established on the internal model principle [3], several

high-performance approaches have been proposed to achieve

high-quality output voltages in three-phase and single-phase

PWM inverters [7]–[23]. Reference [7] proposes a discrete-

time control strategy using a repetitive controller extended

to a proportional–integral (PI) compensator structure in sta-

tionary αβ frame to compensate voltage distortions due to

nonlinear and unbalanced loads. The steady-state performance

is improved by using a 30th-order low-pass ﬁnite-impulse

response (FIR) ﬁlter after implementing the measures to at-

tenuate the high-frequency components so that the voltage

error contains only lower frequencies. However, the proposal

referenced above presents a cancellation issue: the zero at

z =1 (in the discrete-time domain) of the plant introduced

by the transformer cancels with the pole at z =1 of the

repetitive controller, which violates the internal model principle

[3], as demonstrated in [15]. This problem may eventually

lead the transformer to saturation. In [9], the modiﬁed plug-

in repetitive controller combined with the conventional One-

sampling-ahead preview compensator in stationary αβ frame

has been reported to improve the output voltage distortion when

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2121

Fig. 1. Three-phase PWM inverter, ∆Y transformer, ﬁlter, and load.

three-phase rectiﬁer loads are connected at the UPS output.

However, in this case, the output transformer is not considered.

Therefore, connecting an insulating transformer at the inverter

output, a pole–zero cancellation occurs with the plug-in repet-

itive controller in closed loop. In [10], the author proposes

a two-layer voltage controller scheme in synchronous frame

with a PI regulator to ensure zero steady-state error at the

fundamental frequency and a repetitive-based controller with a

high-pass ﬁlter to compensate for the harmonics at the inverter

output voltages. However, inadequate choices of the high-pass

ﬁlter cutoff frequency may result in dc components that can

saturate the transformer at the inverter output. Moreover, the

repetitive controller with a high-pass ﬁlter produces pole–zero

cancellation, which may lead to output transformer saturation.

Other solutions that are also based on the internal model

principle were presented in [11] and [12]. In [11], a three-

layer control scheme is proposed. It consists of a proportional

compensator in stationary αβ frame, an integral controller in

synchronous frame to compensate the fundamental component,

and a selective harmonic compensator in stationary frame based

on a passband FIR ﬁlter with unit gain and zero phase at

the selected harmonics. Reference [12] proposes a robust con-

troller based on the passivity theory framework for three-phase

UPS. This controller guarantees asymptotic stability with good

steady-state performance for nonlinear and unbalanced loads.

Although the controllers proposed in [11] and [12] may be ad-

equate solutions for reducing distortion in output voltages and

for operating with an insulating transformer, the computational

requirements to implement them increase signiﬁcantly with

the number of compensating harmonics. In addition, since the

controller coefﬁcients are not integer numbers, this controller

is sensitive to quantization and roundoff errors, and as a result,

the tracking at selected harmonics is compromised. References

[18] and [19] propose a down-sampled repetitive controller in

synchronous frame with reduced number of poles, which only

compensate odd harmonics in stationary frame. This controller

gives reduced THD output voltages of a three-phase UPS. It

also makes it possible to solve the output transformer satu-

ration; still more due to the slower sampling rate, it is not

necessary to include a zero-phase-shift low-pass FIR ﬁlter [6] to

improve the robustness of the closed-loop system. On the other

hand, [20] proposes an odd-harmonic digital repetitive plug-

in controller to reject these kinds of disturbances in stationary

frame. This odd-harmonic repetitive controller does not have

a pole at z =1 , so it is suitable for operating with an output

transformer. However, a low-pass FIR ﬁlter must be included

in the periodic signal generator loop to reduce the repetitive

frequency gains, and this consequently increases the closed-

loop system robustness. As a result, this ﬁlter compromises

tracking and disturbance rejection.

On the other hand, it is important to emphasize that few

papers explore the UPS transient behaviors. Moreover, few

papers explore the controller transient behaviors using the

discrete-time internal model principle. Hence, to obtain output

voltages with reduced THD and an improved load transient,

this paper proposes a down-sampled internal-model-based con-

troller in synchronous reference frame with a reduced number

of poles. This internal-model-based controller acts together

with a proportional–derivative (PD) predictive compensator,

which has the function to stabilize the closed-loop system. This

compensator results in a simple form for digital implementation

and only requires the measure of the UPS output voltage [15],

[23]. The main feature of the proposed internal-model-based

controller is that it is a straightforward solution for output

transformer saturation. In addition, the reduced number of poles

of the proposed internal model in synchronous frame improves

the transient performance for linear and nonlinear loads as well

as enhancing the stability margin of the closed-loop system.

Thus, it is demonstrated that the transient performance with

the proposed controller can be improved by satisfying the

rigorous output dynamic performance classiﬁcation 1 of the

standard IEC 62040-3, which classiﬁes UPS by performance.

To demonstrate the advantages claimed, the proposed discrete-

time controller structure is digitally implemented in a 16-bit

ﬁxed-point digital signal processor (DSP), and experimental

results in steady state and transient conditions from a 10-kVA

prototype are given.

II. S

YSTEM D ESCRIPTION

A typical double-conversion UPS power circuit is shown in

Fig. 1. Among the three-phase inverter conﬁgurations, the one

2122 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

shown is a strong candidate since: 1) it provides galvanic iso-

lation to the load; 2) it allows the output voltage to be selected

according to customer needs; and 3) it provides a neutral by

the delta-star (∆Y) connection. The dc-bus voltage is almost

constant and supplied by a six-pulse three-phase uncontrolled

diode rectiﬁer, which provides energy to the inverter in normal

operation mode. The dc-to-ac conversion is accomplished by

a space-vector-modulated three-phase three-leg inverter with

insulated-gate bipolar transistor. The high-frequency harmonics

introduced by the modulation are attenuated by the LC ﬁlter. It

is important to point out that the ﬁlter inductors are located at

the transformer primary side so as not to introduce distortions

in the output voltages that result from zero-sequence voltages

produced by unbalanced load currents, which will be shorted

on the delta connection at the transformer primary side [15].

Since this inverter is not capable of controlling zero-sequence

voltages, it is important to minimize the zero-sequence im-

pedance to reduce the distortions in the output voltages. Hence,

the topology in Fig. 1 offers a degree of freedom to minimize

the zero sequence impedance.

III. T

HREE-P HASE PWM I NVERTER, ∆Y T RANSFORMER,

ILTER, AND L OAD M ODEL

A. Stationary Frame Model

From the circuit in Fig. 1, the dynamic equations of the

inverter, transformer, ﬁlter, and load can be obtained by ap-

plying Kirchhoff's laws. To simplify the system modeling, it

is considered that the leakage inductances of the primary and

secondary sides of the transformer are lumped at the secondary

side. The coil resistances are also neglected. The following

equations are then obtained:















2L +



M + L



−L −L

−L 2L +



M +L



−L

−L −L 2L +



M +L

















M + L













(1)











M + L











−

M + L













(2)





˙ v



˙ v



˙ v



















−













. (3)

In these equations, M is the mutual inductance, L is the ﬁlter

inductance, L



is the equivalent leakage inductance, and C



the ﬁlter capacitance. In addition, u

, u

, and u

are the line-

to-line PWM voltages produced by the inverter; v



, v



, and



, and i



, i



, and i



are the phase-to-neutral voltages and

load currents referred to the transformer primary side; and i

, and i

are the phase current in the delta connection.

B. Synchronous Reference Frame State-Space Model

Transforming (1)–(3) to αβ and then to synchronous frame

as in [25], using the linear transformations given in the

Appendix, the state-space model is given by

(t )=

(t )+ B

+ F

, where the matrices A

, and F

are given as







0 − ω 00 − M/D 0

ω 00 0 0 − M/D

00 0 − ω − (3L + M ) /D 0

00 ω 00 − (3L + M ) /D

001 /C 00 − ω

00 0 1 /C ω 0













(M + L

)/D 0

0( M + L

)/D

M/D 0

0 M/D













− 1/C 0

0 − 1/C







. (4)

The state vector has been selected as x

(t )=

]

, and the input and disturbance

vectors as u

(t )=[ u

]

and w

(t )=[ i

]

respectively. In these matrices, D is deﬁned as D =3 LM +

3LL



+ ML



From (1), it is seen that the voltages applied at the trans-

former input are the line-to-line voltages produced by the

inverter. To avoid an additional transformation from line-to-

line to phase voltages that must be performed in the DSP, the

space vector modulation is accomplished using the line-to-line

voltages referred above.

C. Synchronous Reference Frame Discrete-Time Model

To obtain a discrete-time model for the discrete-time con-

troller design, the synchronous frame state equation in the

continuous time domain obtained above is solved throughout a

sampling period T . For this purpose, it is considered that the

control action u

(t) remains constant in a sampling period

T . Thus, the discrete-time state-space equation of the plant

that takes into account the delay of a digital implementation is

given by



(k +1) T

dq_ d

(k +1) T







(kT )

dq_ d

(kT )







(kT ).

(5)

In (5), the additional state variable u

dq_ d

represents the

delayed control action that models the real-time digital

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2123

Fig. 2. Timing chart of DSP controller. T

pwm

: switching period. T : sampling period and PD compensator computing period. T

: time delay. T

: internal-

model-based controller computing period. T

=2 T ,andT

= T .

implementation delay, and the matrices G, H

, and H

are

given as

G = e

= e

(T −T

)

−1

− I)B

= A

−1



(T −T

)

− I



(6)

where T

is the time delay mentioned above, which is related

to a given DSP implementation.

It is important to note that to obtain (5), the sampling of

the variables of interest and the updating of the control law

are performed as shown in the timing chart of Fig. 2. With

this sampling scheme, it is possible to use a low switching

frequency to limit the switching losses while preserving an

acceptable sampling frequency. Also, since sampling is carried

out at zero vectors, the resulting low-frequency harmonics over

the sampled data are reduced when compared with one sample

per sampling period [24].

Since the discrete-time controller proposed here is modeled

using an input–output approach, it is useful to obtain the

input–output description of the plant, which can be found from

(5), by applying the Z transform. Strictly speaking, since the

plant represented by (5) is multiple-input–multiple-output, it is

obtained a sampled transfer function matrix of the system, i.e.,

(z )= C

(z I − G

)

−1

+ D

(7)

where









=[ 0

2×4

2×2

]

=[ 0

2×2

] . (8)

In this case, the resulting sampled transfer function matrix

can be written as

(z )=



(z ) g

(z )

−g

(z ) g

(z )



(9)

where the sampled transfer functions g

(z ) and g

(z ) are given

by the proper rational functions

(z )=

+ b

z + b

− a

+ a

− a

+ a

(z )=

−c

− c

+ c

z + c

− a

+ a

− a

+ a

. (10)

Note that (9) shows that the system presents a cross coupling

given by the transfer functions g

(z ) and −g

(z ). In order

to simplify the controller design, is useful to work with a

single-input–single-output (SISO) system. It is shown that the

inﬂuence of the cross transfer functions is negligible, or in

another words, the system is weakly coupled. It is possible to

see in Fig. 3 that for a large variation in frequency, the transfer

function g

(z ) signiﬁcantly attenuates the output v

when an

input signal in u

is applied or vice versa. Hence, the system can

be treated as a SISO control problem with a transfer function

given by g

(z ) without signiﬁcantly affecting the closed-loop

performance.

In order to deﬁne a proper discrete-time voltage controller for

the plant described by g

(z ), upon the internal model principle

foundation, it is important to show the impact that the zeros of

the plant have in the selection of the controller structure. Fig. 4

shows the zeros of g

(z ).

Fig. 4 shows that this plant presents a pair of zeros at the fun-

damental frequency in synchronous frame, which is associated

with the insulating transformer. These zeros indicate that the

transformer does not transfer the dc component to its output.

This means that an inadequate selection of the discrete-time

2124 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 3. Frequency responses of g

(z ) and g

(z ). T = 198 . 41 µs.

Fig. 4. Zero map of the input–output-sampled transfer function of the

plant g

(z ).

controller may produce a pole–zero cancellation, which causes

any residual dc component from the digital implementation

to be ampliﬁed, which in turn may lead the transformer to

saturate, as demonstrated in [15]. To avoid this problem, a new

discrete-time voltage controller in synchronous frame based on

the internal model principle, and adequate for the system in

Fig. 1, will be described in the next section.

IV. P

ROPOSED D ISCRETE-T IME I NTERNAL-M ODEL-B ASED

C ONTROLLER IN S YNCHRONOUS R EFERENCE F RAME

This section develops the proposed discrete-time voltage

controller based on the internal model principle in synchronous

reference frame. Let us consider the design problem of a SISO

Fig. 5. Discrete-time feedback SISO LTI system.

linear time-invariant (LTI) system in the discrete-time domain

shown in Fig. 5, where the strictly proper transfer function of

the plant is given by g

(z ). The problem is to design a controller

with a proper transfer function g

(z ) so that the feedback

system is asymptotically stable and meets the speciﬁcations of

zero error tracking in steady state even with disturbance signals

present in the plant.

The design procedure, which was developed from the inter-

nal model principle theory presented in [15] for discrete-time

systems, can be summarized in two steps: 1) introduction of

1/φ(z ), a model of the reference and disturbance signals inside

the loop, where φ(z ) is the least common denominator of the

unstable poles of r (z ) and w(z ) and 2) stabilization of the

feedback system using a conventional compensator. It must be

emphasized that neither root of the internal model φ(z ) must be

a zero of the transfer function of the plant so as to ensure the

exact cancellations of the unstable modes of the reference and

disturbance signals.

A. Proposed Internal Model

With the aim of deﬁning an adequate internal model for the

plant g

(z ), ﬁve candidate internal models are presented below.

Fig. 6 shows the pole map of a discrete-time internal model

that is often used in conventional repetitive controllers [5].

When this internal model is implemented in stationary frame,

the pole at z =1 is cancelled with the zero of the plant at

the same location. On the other hand, if this internal model

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2125

Fig. 6. Pole map. Internal model of the conventional repetitive controller [5].

T = 198.41 µs, and 1 /φ (z )=1 /(z

− 1) .

Fig. 7. Pole map. Internal model with poles at odd multiples of 60 Hz.

T = 198.41 µs, and 1 /φ (z )=1 /(z

N/2

+1) .

is implemented in synchronous frame, the same pole–zero

cancellation occurs at 60 Hz. So this particular internal model

is inappropriate for this application as demonstrated in the

experimental result of Fig. 20. It can be seen that the output

phase voltages have the desired levels with a low THD, but

the currents at the transformer primary side appear with a

signiﬁcant offset, which increases continuously, shutting down

the PWM inverter as a result of overcurrents.

Fig. 7 shows a discrete internal model with poles at frequen-

cies that are odd multiples of 60 Hz, while Fig. 8 presents an

internal model with poles at frequencies that are even multiples

of 60 Hz. These internal models have been employed in three-

phase UPS controllers [18], [19] as well as in an odd-harmonic

repetitive controller [20] for single-phase applications [21],

[22]. When the internal model in Fig. 8 is implemented in

Fig. 8. Pole map. Internal model with poles at even multiples of 60 Hz.

T = 198.41 µs, and 1 /φ

(z )=1 /(z

N/2

− 1) .

Fig. 9. Pole map. Internal model with reduced number of poles.

T = 198.41 µs.

synchronous frame, there is no pole–zero cancellation with the

plant. Similarly, the pole–zero cancellation is not a concern

for the internal model of Fig. 7 in stationary frame. On the

other hand, when operating with low switching frequencies, it

is desirable to keep the sampling frequency as high as possible

to improve the closed-loop performance. Usually, T

pwm

=2 T .

In this case, the high gains of the poles close to the Nyquist

frequency may lead to system instability. In order to overcome

this limitation, a zero-phase-shift low-pass FIR ﬁlter can be

included [6] to improve the robustness at high frequencies.

However, this ﬁlter will increase the tracking error and com-

promise disturbance rejection.

Fig. 9, on the other hand, presents an internal model with a

reduced number of poles. In this case, the internal model has

been chosen to compensate the fundamental and the harmonics

2126 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 10. Internal model with reduced number of poles and roundoff error in

coefﬁcients. T = 198 .41 µ s.

Fig. 11. Pole map of the proposed internal model in synchronous frame.

N = T

/2 T , T

=1 /60 , T = 198.41 µs, T

=2 T ,and1/φ

1/(z

N/2

− 1) .

from 2nd to 7th. Note that it is possible to include more poles

if desired. This internal model is adequate for the system in

Fig. 1 since it does not cancel the zeros of g

(z ). However, the

poles of this internal model are sensitive to roundoff errors in

the polynomial coefﬁcients, which are a concern in ﬁxed-point

arithmetic implementation. As a result, the pole location of

the internal model can be signiﬁcantly modiﬁed, as illustrated

in Fig. 10.

Based on the internal models presented above, and having

considered them inadequate for the system in Fig. 1, we now

propose a suitable discrete-time internal model for the plant

(z ). The pole map of the proposed internal model in syn-

chronous frame is shown in Fig. 11. This internal model has

half the poles of the internal model shown in Fig. 8, and no

root of φ

) is a zero of the plant. Also, this proposed

internal model is computed with a reduced sampling rate. As

a result, the Nyquist frequency of the internal-model-based

controller is smaller than the ﬁrst set of harmonics generated

by the switching operation of the PWM inverter, i.e., there are

no internal model poles in the model uncertainty region of the

plant. Note that this internal model results in a reduced compu-

tational effort controller without the roundoff error of the ﬁxed-

point implementation since the coefﬁcients of its polynomial

are integer numbers. Therefore, we propose here a discrete-time

control structure with a faster loop at a sampling period T to

keep a satisfactory sampling rate and a down-sampled internal-

model-based controller. This results in a multirate closed-loop

system, as presented in Fig. 12.

From the two-step design procedure presented at the begin-

ning of this section, the proposed internal-model-based con-

troller, which operate at a sampling period T

=2 T , can be

included in the closed loop. To complete the internal-model-

based controller design, the numerator N

(z ) of the transfer

function G

(z ) shown in Fig. 12 must be selected. To avoid

compromising the simplicity of this controller being consid-

ered, this numerator can be selected as N

)=k

.As

a result, the sampled transfer function of this controller can be

written as

)

, where φ

)=z

N/2

− 1. (11)

In this transfer function, the controller gain k

determines

the convergence time of the voltage error to zero, and the pa-

rameter d is the time advance step size used to compensate the

closed-loop phase at high frequencies [23]. These parameters

must be chosen to ensure the asymptotic stability of the closed

loop and to meet a desired performance.

The next step is to design the conventional compensator

(z ) to stabilize the closed loop with the plant G

(z )= g

(z ).

In this case, a predictive PD compensator has been selected

whose proper transfer function G

(z ) is given as

(z )= k

−1

+ k

−2

. (12)

This compensator has been selected mainly for its simple

structure, which only requires the measurement of the phase

to neutral output voltages. In addition, it provides a signiﬁcant

phase and gain margin to the closed-loop system. The predictive

PD controller gains k

and k

are determined by placement

of the dominant poles of the closed-loop system [23]. It is

important to point out that the tandem connection of G

(z )

with G

(z ) is completely characterized by the proper transfer

function G

(z )G

(z ) since there is no pole–zero cancellation

between G

(z ) and G

(z ), as established in [15].

B. Stability Analysis

Since the closed-loop system operates with two different

sampling rates, the stability analysis can be performed in

two steps.

Step 1: The closed-loop stability of the tandem connection of

the plant with the PD compensator must be ensured. This faster

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2127

Fig. 12. Control structure of the proposed closed-loop multirate SISO discrete-time voltage controller in synchronous frame for axis "d ." z = e

,and

= e

Fig. 13. Closed-loop system. Tandem connection of the plant plus predictive PD compensator.

Fig. 14. Nyquist plot of G

(z )G

(z ). k

=0 .12 , k

= −0. 08,andT =

198.41 µ s.

loop operates with a sampling period T , which results in the

control structure shown in Fig. 13.

To ensure the closed-loop asymptotic stability of the sys-

tem represented in Fig. 13, the roots of the polynomial 1+

(z )G

(z )=0must be inside the unit circle. To demonstrate

that this closed loop is stable, the Nyquist plot of the open-loop

transfer function G

(z )G

(z ) can be used, as shown in Fig. 14.

It can be seen that the tandem connection of G

(z ) with G

(z )

has a large gain margin, which in this case is about 16 dB, and

an inﬁnite phase margin. Therefore, the closed-loop system in

Fig. 13 is asymptotically stable.

Step 2: This step is to ensure the overall stability when the

proposed internal-model-based controller (11) is introduced. To

extend the previous stability criteria to the multirate controller

Fig. 15. Single-rate equivalent of the multirate closed-loop system with a

sampling period T

system in Fig. 12, we transform it to an equivalent system

sampled at slower rate T

. As a result, the equivalent closed-

loop system becomes as that shown in Fig. 15.

The sampled transfer function of the equivalent slow-rate

plant G

) can be found from the equivalent slow-rate

state-space representation of the plant and PD compensator,

which is given in the Appendix. This transfer function can be

expressed as

)

− n

+ n

− n

+ n

− d

+ d

− d

+ d

− d

(13)

The closed-loop stability of the tandem connection of

) with G

) can be proved using the Nyquist

criterion plots of the open-loop transfer function, i.e.,

). Fig. 16 shows the Nyquist plot for

N =42 , k

=1 , and d =1 . It can be seen that the closed-loop

system with an internal-model-based controller remains stable

with a signiﬁcant gain and phase margin.

To demonstrate the beneﬁt of performing the proposed

discrete-time down-sampled internal-model-based controller,

2128 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 16. Nyquist plot of G(z

)=G

). N =42 ,and

= 396.82 µs.

Fig. 17. Nyquist plot of the single-rate system operating at lower sampling

frequency. G(z )=G

(z )G

(z )/ (1 + G

(z )G

(z )) , N =42 , k

=1 ,

d =1 ,andT = 396.82 µ s.

the Nyquist plot of the closed-loop system in Fig. 12, which op-

erates with a single rate at lower sampling frequency, is shown

in Fig. 17. It can be seen that the gain margin stays almost

the same if compared with the gain margin in Fig. 16, but the

phase margin decreases signiﬁcantly when the system operates

at a single rate. Therefore, the stability margin of the proposed

multirate system in Fig. 12 is signiﬁcantly bigger than the

single-rate system at lower sampling frequency, which therefore

represents the beneﬁt of the proposed multirate controller.

Concerning digital implementation, by applying the inverse

Z -transform to (12) and (11), we can obtain the respective re-

cursive difference equations of the predictive PD controller and

the proposed down-sampled internal-model-based controller as

(kT )= k

(k − 1) + k

(k − 2) (14)

imd

(mT

)= k

[mT

− (N/ 2) + d]

+ u

imd

[mT

− (N/ 2)] . (15)

From Fig. 12, we can see that the control law applied to the

plant is given by

(kT )= u

(kT )+ u

imd

(mT

). (16)

Note that (14)–(16) are written for the axis "d "; therefore,

similar equations can be written for the axis "q ." Regarding the

gain, k

must be selected to guarantee a fast convergence of

the voltage error to zero, maintaining the closed-loop system

stability. The values of k

and d are given in Table II. It

is important to emphasize here that simplicity is a signiﬁcant

advantage of the proposed controller if compared with the

controller presented in [11]. It becomes clear by realizing that

the proposed internal-model-based controller implementation

is just (15). In ﬁxed-point arithmetic, the quantization and

rounding errors may result in roots of the polynomial internal

model to be quite different from the desired one (see Fig. 10).

However, since the proposed internal-model-based controller

polynomial coefﬁcients are 1s or 0s, the internal model roots

have low sensitivity to these errors. This is another advantage if

compared with the controllers of [11, eq. (9)] and [12, eq. (27)].

V. S

TEADY-S TATE AND D YNAMIC O UTPUT V OLTAGE

C HARACTERISTICS OF THE UPS

The UPS output speciﬁcations according to IEC 62040-3

must have output voltage dynamic performance characteristics

not exceeding the limits in [1, Figs. 1, 2, or 3] for the application

of increasing/decreasing load steps under linear and reference

nonlinear load for the test conditions in Section 6.3 of this

standard. The objective of classifying UPS by performance is

to provide a common base on which all UPS manufacturer and

supplier data are to be compared. This enables purchasers of

equipment with similar UPS power ratings to compare products

from different manufacturers under the same measurement

conditions.

A. Reference Nonlinear Load Steps in Normal Mode

Step nonlinear loading is deﬁned as the application of the

test circuit, which is shown in Fig. 18, for dissipating the

required steady-state output active power for the percentage

load step relative to the rated steady-state output active power

of the UPS. The load circuit is then ﬁrst deenergized before

application so that its capacitor voltage starts from zero voltage

when applied to the UPS output. To determine the UPS output

dynamic performance, the deviation from the under/overvoltage

limits deﬁned [1] must be obtained. Then, using the test circuit

in Fig. 18, the required step loads (33% of the rated output

apparent power) must be applied or reduced in accordance

with those in [1, Section 6.3.8.5] monitoring the load capacitor

voltage. The capacitor voltage changes should remain within

the stated tolerances in [1, Figs. 1 or 2, Section 5.3.1]. In

Fig. 18, U

is the rectiﬁed voltage, R

is the load resistor set

to dissipate an active power equal to 66% of the total apparent

power, and R

is a series line resistor set to dissipate an active

power equal to 4% of the total apparent power. The procedure

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2129

Fig. 18. Reference nonlinear load test [1].

Fig. 19. Resistive load test [1].

for calculating the passive elements of this reference nonlinear

load is described in [1, Annex E].

B. Linear Load Steps

With the UPS operating in normal mode, a resistive load

equal to 100% of the output active power must be applied in

two steps using the circuit in Fig. 19: one equal to 20% and one

equal to 80%. The step must be performed at the peak value of

the output waveform. Similarly, unloading must be measured

by reducing the load to 20% of the rated output active power by

switching off the 80% load. In both cases, the output waveform

must be observed and stored so as to permit calculation of any

dynamic performance deviation. This deviation is referred as

the rms value above or below the rated value, which is obtained

on a successive half-cycle by half-cycle. The computed values

of this dynamic deviation must remain within the stated limits

in [1, Figs. 1, 2, or 3, Section 5.3.1].

VI. E

XPERIMENTAL R ESULTS

The circuit in Fig. 1 has been tested experimentally to

verify the proposed discrete-time-voltage internal-model-based

controller using a DSP TMS320F241 to control a 10-kVA

UPS. The steady-state load tests have been performed using

resistive linear loads and nonlinear single-phase and three-

phase uncontrolled diode rectiﬁers. The reference nonlinear

load, as described in Fig. 18 and designed according to the

standard IEC 62040-3, has an input series resistor R

=0 .5Ω ,

TABLE I

ETUP PARAMETERS

TABLE II

ONTROLLER P ARAMETERS

Fig. 20. Experimental result. Line current i

at the transformer primary side

with dc component. With the internal model of the conventional repetitive

controller. Output phase-to-neutral voltages. Voltage scale: 50 V/div. Current

scale: 10 A/div. N =84 ,andT = 198.41 µ s. φ(z ) is in Fig. 6.

a load resistor R

=30Ω , and a ﬁlter capacitor C

= 4700 µ F,

and allow to obtain a crest factor of 3. The setup parameters

are given in Table I, and the controller parameters are given

in Table II.

A. Steady-State Performance

Fig. 20 shows the output phase voltages and the input current

at the transformer primary side with a signiﬁcant dc component

when the system in Fig. 1 operates with an internal model

based on the conventional repetitive controller. This fact can

be proven through the harmonic spectrum presented in Fig. 21,

which denote a dc component around 140%. On the other

2130 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 21. Transformer primary side line current harmonics spectrum with dc

component. With the internal model of the conventional repetitive controller.

Fig. 22. Experimental result. Line current i

at the transformer primary

side without dc component. With the proposed internal-model-based con-

troller. Output phase-to-neutral voltages. Voltage scale: 50 V/div. Current scale:

10 A/div. N =42 . φ(z ) is in Fig. 11.

Fig. 23. Transformer primary-side line current harmonics spectrum without

dc component. With the proposed internal-model-based controller.

side, Fig. 22 shows the same waveforms as Fig. 20 with the

system in Fig. 1 operating with the proposed internal-model-

based controller. It can be seen that this current appears without

offset, as demonstrated in the harmonic spectrum of this current

given in Fig. 23, where the dc component is less than 1%,

Fig. 24. Experimental result. Unbalanced linear load. With the pro-

posed controller. Output phase-to-neutral voltages v

, v

,andv

,and

load current i

.THD =0 .7% . Unbalance factor =0 .6%. Voltage scale:

50 V/div. Current scale: 20 A/div.

Fig. 25. Experimental result. Open-loop operation. Three-phase uncontrolled

rectiﬁer at 10 kVA. Output phase-to-neutral voltages v

, v

,andv

,and

load current i

.THD =7% . Voltage scale: 50 V/div. Current scale: 20 A/div.

which can be attributed to sensor error. These tests validate that

the proposed internal-model-based controller does not produce

pole–zero cancellation and consequently does not saturate the

output transformer.

The performance of the proposed controller with linear load

has been tested using an unbalanced resistive rated load con-

nected between a phase and a neutral wire; the experimental

result is shown in Fig. 24. It can be seen that the UPS output

voltages have a low THD as well as a reduced unbalance

factor. On the other hand, Figs. 25 and 26 show the three-

phase line-to-neutral voltages and the nonlinear load current

in phase a, which is drawn by three-phase and single-phase

uncontrolled rectiﬁers, when operating without the proposed

controller. It can be seen that the THD of the output voltages

is very high, around 7% and 10%, respectively. Figs. 27 and 28

show the operation of the proposed controller with the same

nonlinear loads. It is seen that with the proposed controller,

high-quality output voltages are obtained. Also, in Fig. 28, the

single-phase uncontrolled rectiﬁer is connected between one

phase and neutral.

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2131

Fig. 26. Experimental result. Open-loop operation. Single-phase uncontrolled

rectiﬁer at 10 kVA. Output phase-to-neutral voltages v

, v

,andv

and load current i

.THD =9 .8% . Voltage scale: 50 V/div. Current scale:

50 A/div.

Fig. 27. Experimental result. With the proposed controller. Three-phase un-

controlled rectiﬁer at 10 kVA. Output phase-to-neutral voltages v

, v

,and

, and load current i

.THD =0 .8% . Voltage scale: 50 V/div. Current scale:

20 A/div.

Fig. 28. Experimental result. With the proposed controller. Unbalanced load.

Single-phase uncontrolled rectiﬁer at 3.3 kVA. Output phase-to-neutral volt-

ages v

, v

,andv

, and load current i

.THD =1 .2% . Unbalance

factor =0 .92% . Voltage scale: 50 V/div. Current scale: 50 A/div.

This represents the worst case with the phase-rated unbal-

anced nonlinear load. It can be seen from these experimental

results that the THD of the output voltages is very low, which is

around 1%, even with this severe operational condition. Also,

with the proposed controller, the unbalance factor has been

reduced below 1%. The THDs of the UPS output voltages

presented in Figs. 24, 27, and 28 are well below the limits

of IEC 62040-3. In addition, the individual odd and even

harmonics does not exceed the limits of this standard, as shown

in Fig. 29 and Table III.

B. Transient Performance

To verify the transient performance of the UPS output, the

standardized tests described in Section 6.3.7 of the standard

IEC 62040-3 were performed, and the deviations from the

undervoltage and overvoltage limits deﬁned in [1, Figs. 1, 2, or

3] were obtained, as described in Section VI, for nonlinear and

linear loads. Fig. 30 shows the dynamic deviation of the load

capacitor voltage of each phase of the reference nonlinear loads

(Fig. 18) at loading steps. On the other hand, Fig. 31 presents

the deviation of the load capacitor voltage due to the removal

of reference nonlinear loads. Figs. 30 and 31 demonstrate

that the proposed controller satisﬁes the voltage limits under

dynamic conditions not exceeding the undervoltage and over-

voltage transient limits of classiﬁcation 1. Figs. 32 and 33 show

the dynamic deviation of the output voltage rms value when

performing the linear load steps as described in Section VI.

These experimental results again demonstrate that the proposed

controller ensures that the dynamic deviation values do not

exceed the undervoltage and overvoltage transient limits of

classiﬁcation 1 both in the load application and when it is

removed. Thus, this UPS is suitable for feeding most types

of critical loads with high-quality output voltages. The ex-

perimental results for loading and removal of the reference

nonlinear load are presented in the time domain in Figs. 34

and 35. Fig. 34 shows the reference nonlinear load step from

33% to 66%, while Fig. 35 shows the reference nonlinear

removal from 66% to 33%. It can be seen that the undershoot

and overshoot require no more than one fundamental period

before returning to the rated value. It is important to note that

the output voltage transient during the nonlinear load step is

a consequence of the fact that the large reference nonlinear

load capacitor C

is uncharged when it is connected to the

UPS output. Even in this case, the minimum load rectiﬁer

average output voltage value does not exceed the transient

limits imposed by classiﬁcation 1 in [1]. This transient can be

reduced by increasing the inverter output current capability.

The experimental waveforms for the dynamic test with linear

load are presented in Figs. 36 and 37 to complement the

information given by Figs. 32 and 33. Fig. 36 shows the linear

load step from 20% to 80% of the rated output active power,

and Fig. 37 presents the unloading step from 80% to 20%.

VII. S

UMMARY

This paper has proposed a new discrete-time down-sampled

internal-model-based controller in the synchronous reference

2132 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 29. Levels for individual harmonics UPS output voltages with the proposed controller and IEC 62040-3.

TABLE III

EVELS FOR I NDIVIDUAL H ARMONICS UPS O UTPUT V OLTAGES W ITH THE P ROPOSED C ONTROLLER

Fig. 30. Output dynamic performance characteristics of the three-phase UPS. Step reference nonlinear loading from 33% to 66% and from 66% to full load.

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2133

Fig. 31. Output dynamic performance characteristics of the three-phase UPS. Step reference nonlinear removal from 100% to 66% and from 66% to 33%.

Fig. 32. Output dynamic performance characteristics of the three-phase UPS. Step linear loading from 20% to 80% rated active power load.

Fig. 33. Output dynamic performance characteristics of the three-phase UPS. Step linear removal from 80% to 20% rated active power load.

2134 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 34. Experimental result. Output phase-to-neutral voltage v

. Reference

nonlinear load step from 33% to 66%. Voltage scale: 50 V/div. Current scale:

50 A/div.

Fig. 35. Experimental result. Output phase-to-neutral voltage v

. Reference

nonlinear load removal from 66% to 33%. Voltage scale: 50 V/div. Current

scale: 50 A/div.

Fig. 36. Experimental result. Output phase-to-neutral voltage v

. Linear

load step from 20% to 80%. Voltage scale: 50 V/div. Current scale: 50 A/div.

frame, which is adequate for three-phase three-leg PWM in-

verters that operate with an insulating transformer, for UPS

applications. The proposed discrete-time control system results

Fig. 37. Experimental result. Output phase-to-neutral voltage v

. Linear

load step from 80% to 20%. Voltage scale: 50 V/div. Current scale:

50 A/div.

in a multirate system with the plant plus a PD compensator

to stabilize the closed loop in one sampling rate and the

internal-model-based controller with half of the former sam-

pling frequency. This paper demonstrates that, by modifying the

order of the polynomial of the internal model in synchronous

frame, it is possible to ensure that the residual dc components

(in stationary abc frame) are not ampliﬁed, thus avoiding trans-

former saturation. In addition, it is not necessary to include a

zero-phase-shift low-pass FIR ﬁlter in the loop of the internal-

model-based controller. With regard to digital implementation,

the proposed discrete-time controller is an attractive solution

for ﬁxed-point DSPs because it is easy to implement and has

low sensitivity to roundoff error. In addition, for DSP and

microcontrollers with reduced random access memory, this pro-

posed internal model saves the memory space that is required

to store the voltage error in a circular buffer. Furthermore, the

predictive PD compensator that stabilizes the closed loop has

a straightforward design and only requires the measure of the

UPS output voltages. The experimental results presented in this

paper demonstrate that the steady-state output voltages have

high quality under both linear and nonlinear loads with a low

THD and a reduced imbalance factor for unbalanced loads.

In addition, the output voltage dynamic performance of the

three-phase UPS is found to be very good, meeting the severe

classiﬁcation 1 of IEC 62040-3, for both linear and nonlinear

loads.

PPENDIX

The linear transformation that converts the state variables

from the stationary abc to the stationary αβ 0 frame, and from

αβ to dq synchronous frame, is given by

abc_ αβ 0









1 −1/2 −1/2

√

3/2 −

√

3/2

√

21 /

√

21 /

√







αβ _ dq



cos(ωt )sin( ωt)

− sin(ωt )cos( ωt )



. (17)

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2135

The real coefﬁcients of the transfer functions in (10) are

given as

=0 .2276 b

=0 .7325 b

=0 .08777

=0 .2166 b

=0 .03064

=0 .01096 c

=0 .111 c

=0 .008563

=0 .03678 c

=0 .001553

=0 .2007 a

=0 .5854

=0 .06041 a

=0 .09056.

These coefﬁcients have been obtained with a sampling rate of

T = 198.41 µs.

The real coefﬁcients of the closed-loop transfer func-

tion G

) in (13) obtained at 2T = 396 . 83 µsarethe

following:

=1 .01 n

=0 .274 n

=0 .0366

=0 .013 n

=0 .0010 n

=2 .99 × 10

−5

=0 .12 d

=0 .103 d

=0 .012

=0 .0037 d

=0 .00079 d

=5 .23 × 10

−5

=1 .36 × 10

−6

Space-state representation of the single-rate equivalent

closed-loop system in Fig. 15.

Here, we describe the state-space representation of the

single-rate closed-loop system operating at sampling rate T

which has been used to obtain the sampled transfer function

) in (13).

Consider the state-space equations of the plant and the PD

compensator, i.e.,

(k +1) T = G

(kT )+ H

(i, 1)

(kT ) (18)

where G

is given in (8), and H

(i, 1)

is the ﬁrst column of the

matrix in (8), where i =1 , 2 ,... 8. The output of the plant

is given by

(kT )= C

(1,j )

(kT ) (19)

where C

(1,j )

is the ﬁrst row of the C

matrix in (8), and

j =1 , 2 ,... 8. The state variable representation of the PD is

given as

(k +1) T = G

(kT )+ H

(kT ) (20)

where G





, H





, and e

(kT ) is the sampled

voltage error of axis "d" given by

(kT )= r

(kT ) − y

(kT ). (21)

The control action can be written as

(kT )= C

(kT )+ D

(kT )+ u

(mT

) (22)

where C

=[ k

], D

=0 , u

(mT

) is the internal-

model-based control action at sampling rate T

, and x

(kT )=

(k − 1) e

(k − 2)]

. In order to obtain an equivalent

slow-rate state-space representation of the plant plus a PD

compensator at 2T , we can write (18) and (20) as



(k +2) T





(i, 1)

−H

(1,j )





(kT )





(i, 1)

−H

(1,j )

(i, 1)





(kT )





(i, 1)



(k +1)



(i, 1)



(mT

). (23)

Substituting (21) and (22) in (23), we ﬁnd the equivalent

single-rate state-space representation of the system in Fig. 15,

i.e., (24) shown at the bottom of the page.

Finally, the sampled transfer function G

) in (13) can

be obtained by applying the Z transform to (24), which leads to

)=C

I − G

)

−1

(25)

where the matrix C

=[ 0

1×4

1 0

1×5



(k +2) T





− H

(i, 1)

(1,j )

(i, 1)

+ G

(i, 1)

−H

(1,j )

− G

(1,j )

− H

(1,j )

(i, 1)





(kT )





(i, 1)

+ G

(i, 1)

− H

(1,j )

(i, 1)



(k )+



(i, 1)



(k +1)+



(i, 1)

+ G

(i, 1)

−H

(1,j )

(i, 1)



(mT

)



(k +2) T



= G



(kT )



+ H

(k )+ H

(k +1)+H

(mT

) (24)

2136 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

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tive and robust control of UPS," IEEE Trans. Ind. Electron., vol. 48, no. 2,

pp. 334–343, Apr. 2001.

[13] M. Li and Y. Xing, "Digital voltage regulation with ﬂux balance

control for sine wave inverters," in Proc. IEEE APEC , Feb. 2004, vol. 3,

pp. 1311–1314.

[14] H. Pinheiro, F. Botterón, J. R. Pinheiro, H. L. Hey, and H. A. Gründling,

"A digital controller for single-phase UPS inverters to reduce the out-

put DC component," in Proc. IEEE PESC, 2004, vol. 1, pp. 1311–1314.

[15] F. Botterón and H. Pinheiro, "A new discrete-time voltage controller

based on the internal model principle for three-phase voltage source PWM

inverters with ∆Y output transformer," in Proc. IEEE PESC, 2004, vol. 1,

pp. 2508–2514.

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[18] F. Botterón, "Controladores Discretos de Tensão Baseados no Princípio

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sertation, Universidade Federal de Santa Maria—GEPOC, Santa Maria,

Brazil, Dec. 9, 2005.

[19] F. Botterón and H. Pinheiro, "Synchronous frame half-period repetitive

controller for three-phase UPS," in Proc. 8th Brazilian Power Electron.

Conf.—COBEP, 2004, pp. 444–450.

[20] R. Griñó and R. Costa-Castelló, "Digital repetitive plug-in controller for

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PWM inverter for UPS applications," in Conf. Rec. IEEE IAS Annu.

Meeting, Oct. 2001, vol. 4, pp. 2667–2674.

Fernando Botterón was born in Rosário, Argentina,

in 1967. He received the B.S. degree in electri-

cal engineering from the Universidad Nacional de

Misiones, Misiones, Argentina, in 1995, and the

M.S. and Ph.D. degrees in electrical engineering

from the Federal University of Santa Maria, Santa

Maria, Brazil, in 2001 and 2005, respectively.

Since 1996, he has been a Professor in the

Departamento de Electrónica, Universidad Nacional

de Misiones. His research interest includes discrete-

time control and digital modulation techniques ap-

plied to static converters for medium- and high-power uninterruptible power

supplies (UPS).

Dr. Botterón is a member of the Brazilian Power Electronics Society

(SOBRAEP) and the Brazilian Society of Automatic (SBA).

Humberto Pinheiro was born in Santa Maria,

Brazil, in 1960. He received the B.S. degree from the

Federal University of Santa Maria, Santa Maria, in

1983, the M.Eng. degree from the Federal University

of Santa Catarina, Florianópolis, Brazil, in 1987,

and the Ph.D. degree from Concordia University,

Montreal, QC, Canada, in 1999.

From 1987 to 1990, he was a Research Engineer

of a Brazilian UPS company and joined the Pontíﬁcia

Universidade Católica do Rio Grande do Sul, Brazil,

where he lectured on power electronics. Since 1991,

he has been with Federal University of Santa Maria, as an Adjunct Professor.

His research interests are uninterruptible power supplies, wind power systems,

and control applied to power electronics.

... Nas aplicações onde as correntes não são senoidais, como é o caso de filtros ativos de potência ou no caso de conversores alimentando cargas não lineares, o controlador PI-SRF tem seu desempenho comprometido devido ao seu ganho finito nas frequências harmônicas. Neste caso, outros tipos controladores possíveis de serem usados são: (i) controlador PI-SRF com integradores em múltiplas referências rotativas (PI-MRI) [15], (ii) controlador proporcional com integradores senoidais de sinais (P-SSI) [16], (iii) controlador P-SSI no sistema de coordenadas síncrono (P-SSI-SRF) [17], (iv) controlador PI com reguladores ressonantes no sistema de coordenadas síncrono (PI-RES) [18] e (v) controlador repetitivo (RC) [19], [20], [21], [22]. ...

... onde L e R são a resistência e a indutância equivalentes, medidas entre os terminais do conversor e o ponto de acoplamento comum; i a , i b , i c são as correntes de linha sintetizadas No caso das bobinas do transformador serem ligadas em Δ-Y não só os valores de L e R sofrem alterações mas também as relações entre as tensões terminais e as do PAC. Em [19] e [20] são apresentados modelos mais detalhados para o conversor de interface onde, além do tipo de ligação entre as bobinas primárias e secundárias, são propostas soluções para evitar a magnetização assimétrica do transformador em consequência da geração de nível CC nas tensões de saída devido a erros no padrão de chaveamento. ...

... Fazendo z = e jω em (20) e assumindo que as frequências dos harmônicos que distorcem as correntes da Figura 5 estão localizadas mais de uma década abaixo da frequência de Nyquist, pode-se considerar que z −N = e −jωN tem módulo unitário. Portanto, (20) pode ser reescrita de maneira simplificada como segue: ...

This paper presents a simple strategy to compensate the distorted currents synthesized by a grid-connected voltage source converter due to dead-time, turn-on and turn-off time delays of the semiconductor switches. The algorithm considers only the polarity of the fundamental component of the currents flowing through the converter terminals and the values of the time delays and voltage drops supplied by the manufacturers to the semiconductors devices. The presented compensation belongs to the group classified as average value compensation technique methodology since it does not change the pulse pattern of the converter's semiconductor switches. A simplified mathematical description of the effects caused by these unwanted time delays is presented and used to derive a correction factor to be added, in real time, to the converter output controller in order to compensate for its terminal voltages. The asymptotic stability and robustness of the proposed methodology is investigated redrawing the converter current controllers, designed in dq-reference frame, as proportional-resonant ones, in the abc coordinates, and adding the effect of the compensating signal in the feedback loop using the concept of describing function. In addition, the minimum value of the DC bus voltage necessary is also evaluated to ensure the operation of the converter in the linear modulation region when the compensation algorithm is active. Experimental results are presented to validate the theoretical analysis and to demonstrate the effectiveness of the proposed strategy for three different operation conditions of a grid-connected converter: (i) active power injection; (ii) active power consumption and (iii) reactive power support.

... Critical loads such as communication systems, medical equipment and data centers are usually fed by uninterruptible power supply (UPS) systems in case of grid power failures [1], [2]. These loads need high quality power and reliable voltage at their input terminals regardless of voltage anomalies at the grid side. ...

... With the help of (8) and (9), equations (3) and (4) can be rewritten as 1 ...

In this study, a Lyapunov energy function based control method with output voltage feedback loops is proposed for three-phase uninterruptible power supply (UPS) inverters. The presented paper demonstrates that the traditional Lyapunov-energy-function-based control method not only leads to considerable steady-state error in the output voltage, but also distorts the output voltage waveforms. Therefore, a modification has been performed on the traditional Lyapunov-energy-function-based control by incorporating the output voltage feedback loops in the control variables. The robustness of the proposed control method has been studied analytically through transfer functions which are expressed as the ratio of the output voltage to its reference. These analytical results are validated experimentally. In addition, the steady-state and dynamic performances of the proposed control method are also tested experimentally on a three-phase UPS inverter operating with linear (resistive) and nonlinear (diode-bridge rectifier) loads. As a consequence of incorporating output voltage feedback loops into the control variables, the proposed control method offers strong robustness against variations in LC filter parameters, high-quality sinusoidal output voltage along with acceptable total harmonic distortion (THD) values under linear and nonlinear loads, fast dynamic response under abrupt load changes, and negligibly small steady-state error in the output voltage.

... The criterion for the selection of the LC filter parameters at the VSI output was to take a cut-off frequency, a one decade below of switching frequency fsw, for which 1 kHz was chosen. Additionally, to ease the digital control design and to reduce the delay of digital implementation [27], using TMS32028F335, a triangular carrier was used for achieving a sampling frequency fs of 20160 Hz. The LC filter has two functions to attenuate the output voltage ripple and to limit the high-frequency ripple current of VSI IGBTs [28]. ...

... On the other hand, the RL load was selected by the power capacity of the voltage supply in the DC bus and by the maximum current that the electronic sensor board handles at 2A. The non-linear load was designed by the IEC 62040-3 standard to obtain a crest factor of 2.9 [27]. Table 1 shows the inverter characteristics and the test loads values. ...

This article presents a comparative experimental evaluation of some power calculation methods used for three-phase and single-phase systems. In order to make the comparison, methods based on three reference frames, the natural one, αβ and dq, are considered. This paper addresses the experimental comparison for single-phase systems facing sinusoidal and non-sinusoidal waveforms in both linear and non-linear loads. The results are obtained from an experimental platform consisting of a controlled voltage inverter and an acquisition system based on a TMS320F28335, where the power calculation algorithms are implemented. The experimental comparison of the different methods for active and reactive power calculation is made in terms of accuracy and processing time in digital implementation.

... The comparison between standard limit and individual harmonic value of the Γu5L inverter at the nonlinear load in laboratory prototype test is shown in Table 6. According to Figure 20, voltage total harmonic distortion less than 0.6% at linear load and voltage total harmonic distortion less than 2.6% at nonlinear load indicate compliance with IEC620-40-3 [21]. ...

In this article, a modified single-phase five-level photovoltaic inverter is proposed with a single DC voltage source and six semiconductor switches. Compared with the presented inverters, the introduced topology has the advantage of decreased device count and the first switching frequency for high blocking voltage switches. The proposed PV inverter is implemented without clamping diodes and transformers, which leads to a decrement in size and, consequently, the weight of the converter. In addition, for the proposed topology, space vector pulse width modulation (SVPWM) is deployed that reduces the complexity of multilevel modulation. In order to obtain the optimal output voltage of the inverter, the deadbeat controller is suggested as a rapid dynamic, low-computation digital control method. This closed-loop inverter is implemented in TMS320f28335 digital signal controller to evaluate the performance of the proposed inverter under nonlinear and linear loads. Simulation and laboratory prototype results show that IEC 62040-3 harmonic constraints is met for the proposed photovoltaic inverter in standalone applications.

... industriales e informáticos, los cuales requieren una continuidad del suministro de energía eléctrica de manera segura. Los inversores diseñados para alimentar estas cargas deben cumplir con requerimientos de calidad de energía y lograr una buena robustez y fiabilidad, además de una respuesta dinámica de la tensión de salida acorde con las especificaciones impuestas en normas internacionales como por ejemplo la IEC 62040-3 (Botteron and Pinheiro, 2007;Carballo et al., 2016). ...

Este trabajo presenta una estrategia de control digital para inversores trifásicos de cuatro piernas, para cumplir con el requerimiento de normas internacionales de calidad de energía para UPS cuando se alimentan cargas equilibradas y desequilibradas. La estrategia de control propuesta se desarrolla en el marco de referencia dq 0 en tiempo discreto, posee un lazo interno para controlar la corriente de los inductores y un lazo externo para controlar la tensión de salida. Se demuestra que utilizando controladores convencionales pueden desacoplarse las variables de los ejes d y q , lo que permite diseñar los controladores del lazo externo de control de tensión como sistemas SISO independientes, cumpliéndose los requerimientos de régimen transitorio y de régimen permanente impuestos por norma. Para mejorar el desempeño del inversor cuando se alimentan cargas desequilibradas, se propone utilizar un controlador Proporcional-Resonante únicamente en el lazo interno del eje 0, lográndose una estrategia de control simple y de bajo costo computacional. Se presentan resultados de simulación y experimentales que permiten validar la estrategia de control propuesta.

... La predicción del error de corriente permite calcular la acción de control con anterioridad al periodo de muestreo en que debe ser aplicada a la planta. Como resultado de la predicción del error de corriente, la función de transferencia del controlador PD Predictivo presenta dos polos en el origen del plano z y un cero, cuya ubicación se determina en función del valor de las ganancias proporcional y derivativa (Botteron and Pinheiro (2007)). Para lograr el amortiguamiento activo del lazo interno, el cero del controlador se selecciona con una ubicación próxima a z = 0, con el propósito de cancelar el efecto del retardo de transporte asociado a la implementación digital. ...

p>En este trabajo se propone una metodología de diseño del sistema de control de un inversor monofásico para aplicaciones en UPS, que permite cumplir con las exigencias de desempeño de las normas internacionales de calidad de energía IEC62040-3 e IEC61000-2-2. El sistema de control consta de un multi-lazo convencional con controladores del tipo Proporcional-Integral-Derivativo y un Controlador Repetitivo en configuración plug-in con multi-rate (MR-OHRC). La propuesta constituye una metodología de diseño del multi-lazo convencional con la que se reduce la impedancia de salida del inversor y complementa el desempeño del MR-OHRC. De este modo se atenúan las variaciones en la tensión de salida como resultado de perturbaciones producidas por cambios súbitos en la corriente de carga y la alimentación de cargas no lineales. Esta estrategia permite además superar las limitaciones de respuesta dinámica y reducir el tiempo de establecimiento del MR-OHRC. La validez de la propuesta se analiza considerando las exigencias de normas internacionales de calidad de energía en relación a la respuesta dinámica, contenido armónico individual y distorsión armónica, en un prototipo experimental de 2kVA.</p

Abstract A control approach for three‐phase four‐leg LC‐filtered voltage source inverters (VSIs) is proposed for an uninterruptible power supply (UPS) application. A filter inductor in the fourth (neutral) leg of the VSI is considered to enhance the output voltage quality when feeding different types of loads in such a system. The proposed approach is based on the modelling of UPS VSI system in the dq0 synchronous frame. First, the switching functions of the inverter under study are extracted from the achieved system model. Afterward, the control approach is developed by introducing a virtual time constant, which simultaneously affects the system's damping ratio, and a virtual undamped natural frequency in the switching functions. It offers flexibility for improving the system dynamic and steady‐state responses as desired. While the final time constant decreases the transient response time and overshoot, the resulting undamped natural frequency leads to alleviation of steady‐state error in the output voltage. The performance of the proposed control approach is evaluated via SIMULINK‐based and real‐time simulation results.

In this paper, a modified single‐phase five‐level inverter is proposed with a single DC source and six switches. Comparing with the presented converters, the proposed topology has the advantage of reduced device count and the fundamental switching frequency for high blocking voltage switches. The proposed converter implements without clamping diodes and transformers, which reducing the volume, moreover mass of the inverter. In order to achieve the optimum output voltage, the model predictive controller is proposed as a rapid dynamic and semi‐low‐computation digital control system. This closed‐loop system is implemented in TMS320f28335 digital signal processor to assess the performance of the proposed converter under nonlinear and linear loads. Analytical investigation, including simulation and an experimental result, shows compliance with IEC 62040‐3 for inverters in standalone applications.

Jiajie Chang
Lan Xiao

A load current sensorless control strategy using an optimized observer is designed for a three-phase online transformer-based UPS. A closed-loop observer containing state feedback is constructed based on the improved state space model of the inverter circuit. A simple feedback matrix design method is then applied to the observer according to the dead-beat control law, and the load current feedforward control scheme is reconstructed using the proposed observer. This control strategy can save three load current sensors, reduce the THD of the output voltage, and improve dynamic performance. The effectiveness of this strategy is verified by conducting simulation and experiment in a 10 kVA UPS.

Masayoshi Tomizuka

A digital feedforward control algorithm for tracking desired time varying signals is presented. The feedforward controller cancels all the closed-loop poles and cancellable closed-loop zeros. For uncancelled zeros, which include zeros outside the unit circle, the feedforward controller cancels the phase shift induced by them. The phase cancellation assures that the frequency response between the desired output and actual output exhibits zero phase shift for all the frequencies. The algorithm is particularly suited to the general motion control problems including robotic arms and positioning tables. A typical motion control problem is used to show the effectiveness of the proposed feedforward controller.

Repetitive control is formulated and analyzed in the discrete-time domain. Sufficiency conditions for the asymptotic convergence of a class of repetitive controllers are given. The "plug-in" repetitive controller is introduced and applied to track-following in a disk-file actuator system. Inter-sample ripples in the tracking error were present when the "plug-in" repetitive controller was installed. The performance is enhanced, however, when the zero-holding device is followed by a low- pass filter or replaced by a delayed first-order hold.

Bruce A. Francis
O.A. Sebakhy
Walter Wonham

For the multivariable control system described by [(x)\dot] = Ax + Bu,y = Cx,z = Dx\dot x = Ax + Bu,y = Cx,z = Dx (wherey is the measured output andz the output to be regulated) conditions are given for the existence of a controller which preserves output regulation and loop stability, in the presence of small parameter variations in controller and plant. Under mild conditions, such a strong synthesis is shown to exist if and only if the regulator problem with internal stability (RPIS) is well-posed. Synthesis is achieved by means of a feedback configuration which in general incorporates an invariant, and suitably redundant, copy of the dynamic model adopted for the exogenous disturbance and reference signals which the system is required to process.

This paper proposes a new two layers digital controller for PWM inverters, which significantly reduces the output DC voltage component. It is suitable for low cost PWM inverters where analog-to-digital converters and digital pulse width modulators with small numbers of bits are used. The controller description and design are presented. Experimental results on a 5 kVA set-up validate the theoretical analysis carried out.

In this paper a new digital voltage controller based on the internal model principle for three-phase inverters with Δ transformer at the output is proposed. A dynamic model of the inverter, transformer, filter and load is derived and a decoupling method is proposed. The proposed digital controller is not prone to produce DC components, which that can lead to the output transformer saturation. Additionally, this digital controller result in a simple form and it is well suited for a fixed-point implementation. Experimental results, implemented in 16 bits DSP TMS320F241, validate the theoretical developments and demonstrate the good performance of the proposed controller under both nonlinear balanced and unbalanced loads.

Kok Kia Chew
Masayoshi Tomizuka

Perfect regulation may be too stringent a condition in repetitive control. In this paper, the rigid stability requirement is relaxed by including an appropriately chosen filter in the repetitive signal generator. Lacking an internal model, perfect regulation is not assured in the modified system. The steady-state and stochastic performances of the resulting system are analyzed. These analyses reveal that under certain conditions the dual objectives of good steady-state and stochastic performances are conflicting. A high repetitive gain may give good steady-state performance, but the variance propagation of stochastic disturbances is large (extremely large for some choice of a parameter in the modified controller).

This work develops a digital repetitive plug-in controller for odd-harmonic discrete-time periodic references and disturbances. The controller presents a novel structure and it has a lower data memory occupation than the usual repetitive controllers because it takes advantage of the particular characteristics of the signals to track or attenuate. A sufficient criterion of stability, several hints for its practical application and an example are also included in the work.

Keliang Zhou
Kay-Soon Low
Soon-Hie Tan
Yong-Qiang Ye

In this paper, an odd-harmonic repetitive control scheme with phase lead compensation is proposed for CVCF PWM converters. The proposed repetitive controller that combines an odd-harmonic periodic generator with a poles-zeros-cancellation phase lead filter occupies less data memory that a conventional repetitive controller does. And it offers faster monotonic convergence of the tracking error; and yields nearly exact tracking accuracy (very low THD and tracking error RMS). Analysis and design of such an odd-harmonic repetitive control system are completely discussed. Simulation results of a single-phase PWM inverter with proposed repetitive controller are illustrated to validate the proposed approach.

Mingzhu Li
Yan Xing

A novel digital voltage regulation based on digital signal processor is proposed in the paper. According to the difference between digital-controlled and analog-controlled inverters, the reasons causing dynamic flux imbalance of output transformer are analyzed in detail. To avoid the infection of truncation error, which is one of the most predominant ingredient leading to flux imbalance in digital-controlled systems, methods used to guarantee the symmetry of the output of voltage regulator are proposed. And then a valid solution for flux balance by sampling the instantaneous primary current of the output transformer and introducing the on-line calculated bias current component into the voltage regulation arithmetic is presented. Design guidelines are provided and experimental results verify the excellent performance of the proposed method.

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